// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -emit-llvm %s -o - \
// RUN:     | FileCheck %s  -check-prefix=RV32ZKND

// RV32ZKND-LABEL: @aes32dsi(
// RV32ZKND-NEXT:  entry:
// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
// RV32ZKND-NEXT:    ret i32 [[TMP2]]
//
int aes32dsi(int rs1, int rs2) {
  return __builtin_riscv_aes32dsi_32(rs1, rs2, 3);
}

// RV32ZKND-LABEL: @aes32dsmi(
// RV32ZKND-NEXT:  entry:
// RV32ZKND-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKND-NEXT:    [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZKND-NEXT:    store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
// RV32ZKND-NEXT:    store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
// RV32ZKND-NEXT:    [[TMP2:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
// RV32ZKND-NEXT:    ret i32 [[TMP2]]
//
int aes32dsmi(int rs1, int rs2) {
  return __builtin_riscv_aes32dsmi_32(rs1, rs2, 3);
}
